IC chips are fragile, and cannot be exposed to air and particles which may cause destruction of the chips. As shown in FIG. 1, an IC chip 2 is glued by an epoxy paste 3 to an IC package 4 and encapsulated to protect the chip 2 from air and particles. Wires 6 connect the IC chip 2 to leads 8 of the IC package 4 for connection to a printed circuit board (not shown).
During a final stage of manufacturing of the IC package 4, a bonding device diagram 10, as shown in FIG. 2A, is required to show the wire connections 12 between a plurality of die pads 14 forming a die pad ring 15 at the periphery of a die image plot 18 (see also FIGS. 2B and 2C) and bond fingers 16 which are generally connected to the leads 8 of the package 4. Using the bonding device diagram, the wires 6 are connected between the die pads 14 and the bond fingers 16 during manufacture of the packaged IC.
The term "build sheet," i.e., a paper sheet instructing how to build, is generally used to refer to the bonding device diagram. In the first step of making the build sheet, a design engineer plots out the die image plot 18, as shown in FIG. 2B, of an IC chip 2 which has been designed and is ready to be manufactured. The die image plot 18 is an enlarged image of the IC chip 2 which is plotted out as large as possible on a 8.5".times.11" paper to the same scale as a blank bond master (described hereinafter) which can be in a scale of up to 20 or more times the actual IC chip size. Thereafter, the design engineer contacts a package engineer for the availability of an existing package for the IC chip 2. To save costs and production time, an existing package is preferable to a redesigned package or a new package.
There are nine general package families:
(1) Plastic Quad Flat Pack (PQFP); PA0 (2) Pin Grid Array (PGA); PA0 (3) Plastic Leaded Chip Carrier (PLCC); PA0 (4) Leadless Chip Carrier (LCC); PA0 (5) Plastic Dual Inline Package (PDIP); PA0 (6) Ceramic Dual Inline Package (CERDIP); PA0 (7) Thin Small Outline Package (TSOP); PA0 (8) Small Outline Integrated Circuit Sidebraze (SOIC); and PA0 (9) Ceramic Quad (Cerquad).
As can be appreciated, the nine package families are exemplary, and not exclusive, since other package families exist or may be developed. Since each package family includes hundreds of different types of package layouts, sizes and lead count, each package engineer is assigned to know a certain number of package families.
If the design engineer is able to reach the package engineer, the design engineer informs the package engineer of the number of die pads 14 and the X and Y dimensions of the actual die size of the IC chip 2. The package engineer determines if the IC chip 2 will fit into a particular package based on the actual die size, and determines whether the die pads 14 can be bonded to the bond fingers 16 of a particular package based on the number of die pads 14.
Once an appropriate package has been chosen, the package engineer uses an AutoCAD program to draw an internal artwork 20 of a lead frame of the package, i.e., the outline of a central portion of a lead frame drawing 22. As shown in the lead frame drawing 22 of FIG. 2D, a series of lead frames is formed on a strip of metal with portions or sections of metal removed to define metal areas forming the bond fingers 16, die attach area 24, tiebar 26, leads 8, etc. The internal artwork 20 thereafter is expanded as much as possible on 81/2".times.11" paper to form a blank bond master, as shown in FIG. 2E.
However, the scales of the die image plot 18 of FIG. 2B and the blank bond master 28 of FIG. 2E have to be the same. For example, if the internal artwork 20 with the blank bond master 28 is 16 times the actual size, the die image plot 18 has to be 16 times the actual size. To achieve the same scale, a technician expands or shrinks the die image plot 18 and/or the internal artwork 20 using a photocopying machine. Thereafter, the technician uses a ruler to measure the dimensions of the photocopied internal artwork and die image plot. If the scales are not correct, the technician re-expands or reshrinks the die image plot and/or internal artwork and remeasures the dimensions. Such a process is repeated until the scales are the same. Repeated photocopying and remeasuring is time consuming and wasteful.
The blank bond master 28 outlines the die attach area 24, bond fingers 16 and the tiebar 26. The die attach area 24 is a metallic plate where the IC chip 2 will be glued during manufacturing of the IC package 4. The bond fingers 16, which are numbered, for example, from 1 through 20, are generally coupled to the leads 8, and the wires 6 connect the die pads 16 of the IC chip 2 to the bond fingers 16.
For PLCC packages, the lead frame drawing 22 is also used to properly align the blank bond master 28. The top single hole 30 and the two bottom holes 32 of the lead frame drawing 22 indicate the top and bottom of the lead frame, and "PIN 1" corresponds to bond finger 1. Without the lead frame drawing 22, the blank bond master 28 can be misaligned and the bond fingers 16 mislabeled before the wire bond. As can be appreciated, the same or different methods of alignment and labelling can be used for other package families.
Prior to gluing the die image plot 18 onto the blank bond master 28, the technician uses a ruler to measure X and Y die attach clearances, as shown in FIG. 2G, to meet the minimum requirement for the particular IC chip. The measured die attach clearance is divided by the scale to which the die image plot 18 and the bonding device diagram 10 have been expanded to arrive at the actual die attach clearance. The technician needs to experiment with the placement of the die image plot 18 on the die attach area 24 to assure that the die attach clearances are equal on each side and with top and bottom. The die image plot 18 is then glued onto the blank bond master 28, as illustrated in FIG. 2G.
Such die attach clearance is required to compensate for the overflow of the epoxy paste 3 during actual manufacturing of the IC package 4. Without the die attach clearances in PLCC packages, for example, the paste 3 may flow over the edge of the die attached area 24 and may act as particles to cause reliability problems. Generally, a large die attach clearance is preferable. However, the length of the wire 6 connecting the bond fingers 16 to the die pads 14 increases with increase in the die attach clearance. If a wire 6 is too long, the wire 6 will sag, rather than loop, as shown in FIG. 1, causing reliability problems. Hence, the die attach clearance and the wire length are counteractive, and a balance must be achieved between the die attach clearance and the wire length.
After the proper placement of the die image plot 18 on the blank bond master 28, multiple copies of the overlaid die image plot 18 and blank bond master 28 are made to preserve the original, and the design engineer uses a pencil and/or pen to draw the wire connections 12 between the bond fingers 16 and the die pads 14 to achieve the bonding device diagram 10, as illustrated in FIG. 2A. The drawing of the wires 12 is called "bonding on paper," which corresponds to the bonding of the wires 6 between the die pads 14 and the bond fingers 16 during manufacture. The letters N/C indicate no wire connection to a die pad 14 or a bond finger 16.
The bond fingers 16 or the die pads 14 can have a single bond, a double bond, a triple bond, etc. In FIG. 2A, for example, bond finger 1 is connected to two die pads, and hence, bond finger 1 is said to have a double bond and each die pad has a single bond. Two wires connect bond finger 6 to a single pad in the bonding device diagram, i.e., double bond to bond finger 6 and the die pad. When three wires connect bond finger 15 to three different die pads, bond finger 15 has a triple bond, and each die pad has a single bond. As can be appreciated, numerous variations of the wirebond are possible between the bond fingers and the die pads. Further, the number of die pads to the number of bond fingers can be the same or different.
Manual drawing of the wires causes various problems. As shown in the figures, the die pads 14 are very small areas even when the die image plot 18 is an expanded view of the actual IC chip 2. The die image plot 18 illustrated in FIG. 2B has approximately 80 die pads, and presently, the number of die pads ranges from 8 to 242. Even with an expanded die image plot, the die pads are very difficult to accurately locate and determine due to smearing of the die pad ring 15. The problem becomes severe as the number of die pads 14 increase. As can be appreciated, manual drawing of the wires 12 from the die pads to the bond fingers is extremely cumbersome and may be illegible.
As discussed above, the die attach clearance also must be sufficient to compensate for overflow of the epoxy paste, and a large die attach clearance is preferable. A larger die attach clearance increases the wire length, but wire length cannot exceed a maximum length to prevent sagging. To assure a proper wire length, the design engineer uses a scaled ruler to measure the length of the drawn wires to determine the actual length. If the maximum length is exceeded, the engineer has to redraw the wire and repeated drawing of the same wire may be required. The design engineer must also assure that no wires cross or touch one another to prevent shorting. If the design engineer encounters a situation where a wire crosses or touches another wire to connect a die pad to a bond finger, the engineer may be required to redraw one or all of the wires to assure that no wires cross or touch, and repeated drawing may be required. Such a process is time consuming.
The manual process of the build sheet also does not account for factors which occur during the actual manufacture of the IC package. One of the factors is the width of the wire 6 compared to the width of the die pad 14 and the bond finger 16. Although it is possible to draw multiple wires to a single die pad or bond finger, such bonding may not be possible during manufacturing. The width of the wires 6 may be too large for multiple bonding to a die pad 14 or a bond finger 16. Hence, multiple wires may not fit onto a single die pad or bond finger for a double bond, a triple bond, quadruple bond, etc. As a general rule, a single wire can be bonded to a properly designed die pad and bond finger meeting minimum design rules. The occurrence of such a problem may stop the manufacturing of the IC chip, and a new bonding device diagram becomes required prior to restarting the manufacturing process.
Further, the bonding device diagram 10 is a two dimensional drawing of the connection, and hence, the wire connections 12 from the die pads 14 to the bond fingers 16 in the bonding device diagram 10 are in a straight line. However, as shown in FIG. 1, the wires 6 are looped in three dimensions, and a bond wedge or tail (not shown) is created at the end of the wire 6 bonded to the die pad 14. Assuming that there is an imaginary vertical line perpendicular to a die pad 14, an angle between the imaginary vertical line and the looped wire must stay within a certain range. The bond wedge may cross over to the next die pad if the angle is too large, and cause "shortout" of the IC chip 2. The manual process of the build sheet creation does not account for such a factor, and the manufactured IC chip with exceeded angle may have to be discarded.
On the bonding device diagram 10, the engineer types in the dimension of the die attach area 24 in inches, and if the dimension of the die attach area 24 is in microns, the engineer must also indicate the inch equivalent. Other information, such as the device number and metal mask number of the lead frame, must be provided on the bonding device diagram 10 prior to sending the bonding device diagram 10 for approval. Manual insertion of such information is also time consuming.
The integrated chip is then packaged using the approved bonding device diagram as a reference for bonding the wires. As discussed above, various problems may arise due to the bonding device diagram inaccurately showing the wire connections 12 between the die pads 14 and the bond fingers 16. The problem may be undiscovered during the manufacturing process, leading to reliability problems when the IC package is connected to the printed circuit board. Further, if the problem is discovered, the manufacturing process may be delayed until a new bonding device diagram is provided. As can be appreciated, even the revised bonding device diagram may have problems, and the bonding device diagram may have to be created over and over again until the problems discussed above have been corrected.
The conventional manual process of the build sheet is inefficient, costly, and illegible. The present invention solves the shortcomings of the conventional process.